`ifndef PC_REG_V
`define PC_REG_V


`include "defines.v"

// PC 寄存器
module pc_reg(
    input  wire                         clk     ,
    input  wire                         rstn    ,

    output reg[`InstAddrWidth - 1 : 0]  pc_o
);

always @(posedge clk or negedge rstn) begin
    if(rstn == 1'b0) begin
        pc_o <= 'd0;
    end
    else begin
        pc_o <= pc_o + 4'd4;
    end
end

endmodule


`endif // PC_REG_V